On-line test of embedded systems: which role for functional test?
Matteo Sonza Reorda, Professor in the Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
On-line test of embedded systems is becoming increasingly important mainly due to the growing usage of electronic systems in safety-critical applications and to the higher chances of failures in new devices. Standards and regulations are also pushing the adoption of effective on-line test solutions both at the device and at the system level. While Design for On-Line Testability is definitely an effective solution, there are situations in which alternative or complementary ways have to be explored, and functional testing stands as the only viable solution. The presentation will overview the main open issues in this area (e.g., in terms of achievable defect coverage, test time, and costs), emphasizing the limitations of the functional approach, but also reporting about recent advancements that could allow its easier and wider adoption in practice.
TSV Based 3D Stacked ICs: Opportunities and Challenges
Said Hamdioui, Professor, Computer Engineering Laboratory, Delft University of Technology, Delft, the Netherlands
The industry is preparing itself for three-dimensional stacked ICs (3D-SICs), vertically interconnected by means of Through-Silicon Via's (TSVs). 3D-SIC is an emerging technology that promises huge advantages such as heterogeneous integration with higher performance and lower power dissipation at a smaller footprint. However, for 3D integration to become a viable product approach, many challenges have to be solved including design, manufacturing and test.
This talk will provide first an overview about the opportunities and challenges of 3D-SICs. Thereafter, some major challenges such as yield improvement, reliability and test cost reduction will be addressed in more details. Compound yield is a major concern for Wafer-to-Wafer 3D stacking (used for e.g. dies with similar size such as memories), especially for higher number stacked dies. Reliability is another concerns that may be caused due to wafer thinning, TSV processing, thermal and mechanical stress, etc. Finally, 3D-SIC test needs complex test flow trade-offs due to e.g. huge different test moments (e.g., pre-bond test, mid-bond test, final test).
Professor Hamdioui (http://ce.et.tudelft.nl/~said/) received the MSEE and PhD degrees (both with honors) from the Delft University of Technology (TUDelft), Delft, The Netherlands. He is currently co-leading dependable-nano computing research activities within the Computer Engineering Laboratory of TUDelft. Prior to joining TUDelft, Hamdioui worked for Microprocessor Products Group at Intel Corporation (CA, USA), for IP and Yield Group at Philips Semiconductors R&D (France) and for DSP design group at Philips/ NXP Semiconductors (Nijmegen, The Netherlands). His research interests include dependable nano-computing and VLSI Design & Test (defect/fault tolerance, reliability, security, nano-architectures, Design-for-Testability, Built-In-Self-Test, 3D stacked IC test, memory test, defect oriented test, etc.) Professor Hamdioui published one book and co-authored over 100 conference and journal papers. He is strongly involved in the international test technology community. He delivered dozens of keynote speeches, distinguished lectures, and invited presentations and tutorial at major international forums/conferences and at leading semiconductor companies. Hamdioui is a Senior member of the IEEE.
Vertical Slit Transistor based Integrated Circuits (VeSTICs)
Andrzej Pfitzner, Professor of the Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Poland
Vertical slit 3D device architecture, proposed by W. Maly, can be shared by a variety of different types of transistors including a new junctionless N-channel and P-channel vertical slit FET (VeSFET). VeSFETs have two symmetrical independent gates that provide many new circuit level opportunities e.g. in energy conservation domain, unavailable otherwise. The key feature of the new architecture is its extreme regularity, which promotes highly repetitive layouts, constructed with small number of
massively replicated simple geometrical patterns vastly simplifying critical lithography steps. A single layer of VeSFETs is a canvas for Vertical Slit Transistor based Integrated Circuits (VeSTICs). Proposed new IC design/manufacturing paradigm can deliver high manufacturing efficiency (as has been achieved by memory producers) combined with fast and inexpensive design.