Embedded Tutorial I
3D Integration: Opportunities, Design Challenges and Approaches.
Uwe Knöchel (Fraunhofer IIS/EAS, Germany)
More than Moore technologies like 3D-integration enable the dense integration of different circuits. With the right partitioning of functional units in a die stack; the system performance can be increased and the power consumption reduced. Design of 3D-integrated systems requests the consideration of several electrical and multi-physical interactions in a stack, e.g. thermal management, power distribution and electromagnetic compatibility stronger than in 2D-SoC-design. Therefore new design flows and tools are under development. The tutorial outlines the current status of technologies and applications for 3D-integration and gives an overview on the design challenges. Approaches for 3D design-flow and algorithms will be presented.
Embedded Tutorial II
Asynchronous Circuit Design: From Basics to Practical Applications.
Eckhard Grass, Milos Krstic, Xin Fan, Steffen Zeidler (IHP GmbH, Germany)
After motivating asynchronous techniques in general, the main advantages and disadvantages will be discussed. Several asynchronous timing models such as delay insensitive (DI) quasi delay insensitive (QDI) and speed independent (SI) will be presented and compared. Completion-detection methods used in asynchronous design are reviewed.
The benefits and trade-offs of the globally-asynchronous locally-synchronous (GALS) approach are highlighted. A design flow and useful design tools for asynchronous- and GALS design are presented. Especially in mixed signal circuits, electro-magnetic interference (EMI), supply voltage fluctuations and ground bounce are critical issues. Special techniques for the reduction of those effects will, therefore, be discussed.
For practical industrial applications the testability of ASICs and the test effort has a significant impact on their final cost. Consequently, efficient test strategies are required and will be evaluated in the tutorial. Finally, several asynchronous demonstrator ASIC designs are presented. An outlook on the application of asynchronous design techniques in future is provided.
Embedded Tutorial III
Automated Synthesis and Design-Error Repair of Systems.
Georg Hofferek (Graz University of Technology, Austria)
Due to the ever increasing complexity of digital systems, the need for formal verification methods has also been increasing steadily. Verification usually requires some form of specification. Having available a formal specification for a system, one can ask why designers have to bother fixing errors that have been detected. Or, going one step further, why not synthesize the entire system from the specification? We will have a look at two state-of-the-art automated and
correct-by-construction synthesis methods that address these questions. First, we will consider property synthesis, which can be viewed as a game. Second, we show how to benefit from abstraction by uninterpreted functions.
Embedded Tutorial IV
Fault management in an IEEE P1687 (IJTAG) environment.
Erik Larsson (Lund University, Sweden) and Konstantin Šibin (Testonica Lab, Estonia)
To meet the constant demand for performance, it is increasingly common with multi-processor system-on-chips (MPSoCs). As these integrated circuits (ICs) may contain billions of transistors squeezed on a few square centimeter, it is difficult to ensure that they are correct. Defects may escape manufacturing test or develop during operation and, further, ICs manufactured in later semiconductor technologies are increasingly sensitive to environmental disturbances. These defects may be permanent (hard) or transient (soft).
To enable graceful degradation, fault management can be applied to handle eventual defects. Fault management include collection of error statuses from each of the processors, classify the defects, fault mark defective processors, schedule jobs on non-defective processors.
This tutorial consists of three parts. First, we will discuss the need of IEEE P1687 (IJTAG), a standardized mechanism to access embedded features. Second, we will discuss how to make use of IEEE P1697 for fault management. And, third, we will make a demonstration of a fault management solution that makes use of IEEE P1687.